Case Study On Barrel Shifter
- To maintain accuracy without the benefit of a floating-point data path, fixed-point DSP processors have a good support for shifting operations. Many DSPs provide barrel shifters at both the input (pre-scaling) and output (post-scaling) of their MAC logic.
- The pre-scaler is generally activated by a pseudo instruction used in the code, for example, MACD, X, Y, 4, which divides the input data by 4 BEFORE the multiply occurs. The coefficient remains unaltered.
- An output post-scalar is generally set up prior to execution of a block of code (i.e., digital filtering, convolution, or an FFT) in order to scale the output data from the MAC operation by a specific factor.
- This is intended to reduce the probability of overflows, which can occur during long sequences of MAC operations.
- Use of this automatic scaling technique partially eliminates the overheads otherwise incurred when having to check your results for overflow and underflow (the DSP generally provides one or two flags, which need to be checked manually for overflow and underflow by your program after each MACD execution).
- If an overflow is indicated, you can either abort the program or recalculate the results.
2. Normalization & Denormalization:
- It is indicated, you can either abort the program or recalculate the results.
- Normalization involves conversion from fixed point to floating point systems by the generation of mantissa and exponent.
- This is a two process.
- The first one involves exponent detection which calculated the number of shifts needed.
- The next step provides this value to the shifter for actually shifting the number. Denormalization involves the conversion of floating point into fixed point systems i.e. the inverse of normalization.
- The exponent provides a number of shifts required in the mantissa.
- A block floating-point format enables a fixed-point processor to gain some of the increased dynamic range of a floating-point format without the overhead needed to do floating-point arithmetic. However, some additional programming is required to maintain a block floating-point format.
- It can also be used in floating point processors.
DATA ADDRESS GENERATORS
- Super Harvard Architecture with modifications is the most suited Architectures for DSPs.
- Such an architecture has multiple busses to access the memory viz. Data memory bus & program memory bus.
- This is obviously an advantage with respect to increasing in speed but this would demand additional hardware that would keep track of address on each of these busses.
- The Data Address Generator (DAGs) keeps a track of the addresses of the input data and the coefficients that are stored in the data and program memories respectively.
- Now the CPU no longer has to bother about the addresses of the data, the DAG will do that task.
- This is most useful when a set of addresses are used repeatedly, for example, scanning a data array or in FFT computations.
- The address generation unit would require its own arithmetic unit to increment or decrement the addresses, and/or to add/subtract offsets from the base address in case of non-sequential addresses.
- The increment/decrement step size for an address in each case can be predefined as 1,2,4 or 8 and so on depending upon the size of each data item. Any DAG would require at least the following types of registers. The types of registers are:
•Length and Base registers: Length and base registers setup the range of addresses and the starting address for a circular buffer. These registers hold the values that the DAG uses for generating addresses.How to configure DSP processor
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